Classes
struct	stDmaWrapper_Roi
	Roi Properties. More...

struct	stDmaWrapper_FrameProp
	Frame Properties. More...

struct	stDmaWrapper_RoiAlignInfo
	Roi alignment. More...

struct	stDmaWrapper_DmaTransferSetup
	DmaTransferSetup Properties. More...

Macros
#define	HALIDE_HEXAGON_ENUM enum __attribute__((aligned(4)))
	Format IDs.

#define	PW_MIN_SVS 0
	Power Corner vote.

#define	PW_SVS2 1

#define	PW_SVS 2

#define	PW_SVS_L1 3

#define	PW_NORMAL 4

#define	PW_NORMAL_L1 5

#define	PW_TURBO 6

Typedefs
typedef uint16_t	uint16

typedef uint32_t	uint32

typedef int32_t	int32

typedef unsigned long	addr_t

typedef unsigned int	qurt_size_t

typedef unsigned int	qurt_mem_pool_t

typedef void *	t_stDmaWrapperDmaStats
	DMA status Currently not use, for future development.

typedef HALIDE_HEXAGON_ENUM	eDmaWrapper_TransationType
	Transfer type.

typedef struct stDmaWrapper_Roi	t_StDmaWrapper_Roi
	Roi Properties.

typedef struct stDmaWrapper_FrameProp	t_StDmaWrapper_FrameProp
	Frame Properties.

typedef struct stDmaWrapper_RoiAlignInfo	t_StDmaWrapper_RoiAlignInfo
	Roi alignment.

typedef struct stDmaWrapper_DmaTransferSetup	t_StDmaWrapper_DmaTransferSetup
	DmaTransferSetup Properties.

typedef void *	t_DmaWrapper_DmaEngineHandle
	Handle for wrapper DMA engine.

Functions
void *	HAP_cache_lock (unsigned int size, void **paddr_ptr)
	Abstraction for allocation of memory in cache and lock.

int	HAP_cache_unlock (void *vaddr_ptr)
	Abstraction for deallocation of memory and unlock cache.

t_DmaWrapper_DmaEngineHandle	hDmaWrapper_AllocDma (void)
	Allocates a DMA Engine to be used by using the default wait type (polling).

int32	nDmaWrapper_FreeDma (t_DmaWrapper_DmaEngineHandle hDmaHandle)
	Frees a DMA Engine that was previously allocated by AllocDma().

int32	nDmaWrapper_Move (t_DmaWrapper_DmaEngineHandle hDmaHandle)
	Starts a transfer on the provided DMA engine.

int32	nDmaWrapper_Wait (t_DmaWrapper_DmaEngineHandle hDmaHandle)
	Blocks until all outstanding transfers on the DMA are complete.

int32	nDmaWrapper_FinishFrame (t_DmaWrapper_DmaEngineHandle hDmaHandle)
	This call flushes the DMA buffers.

int32	nDmaWrapper_GetRecommendedWalkSize (t_eDmaFmt eFmtId, bool bIsUbwc, t_StDmaWrapper_RoiAlignInfo *pStWalkSize)
	Get the recommended walk ROI width and height that should be used if walking the entire frame.

int32	nDmaWrapper_GetDescbuffsize (t_eDmaFmt *aeFmtId, uint16 nsize)
	Calculates the HW descriptor buffer size based on the formats that will be used with the engine.

int32	nDmaWrapper_GetRecommendedIntermBufStride (t_eDmaFmt eFmtId, t_StDmaWrapper_RoiAlignInfo *pStRoiSize, bool bIsUbwc)
	Get the recommended (minimum) intermediate buffer stride for the L2 Cache that is used transfer data from/to DDR.

int32	nDmaWrapper_GetRecommendedIntermBufSize (t_eDmaFmt eFmtId, bool bUse16BitPaddingInL2, t_StDmaWrapper_RoiAlignInfo *pStRoiSize, bool bIsUbwc, uint16 u16IntermBufStride)
	Get the recommended intermediate buffer size for the L2 cache that is used to transfer data to/from DDR.

int32	nDmaWrapper_DmaTransferSetup (t_DmaWrapper_DmaEngineHandle hDmaHandle, t_StDmaWrapper_DmaTransferSetup *stpDmaTransferParm)
	Setup Dma transfer parameters required to be ready to make DMA transfer.

int32	nDmaWrapper_PowerVoting (uint32 cornercase)
	DMA power voting based on Cornercase.

Variables
	HALIDE_HEXAGON_ENUM {QURT_EOK = 0}
	Format IDs.

Macro Definition Documentation

◆ HALIDE_HEXAGON_ENUM

typedef HALIDE_HEXAGON_ENUM enum __attribute__((aligned(4)))

Format IDs.

Definition at line 17 of file mini_hexagon_dma.h.

◆ PW_MIN_SVS

#define PW_MIN_SVS 0

Power Corner vote.

Definition at line 28 of file mini_hexagon_dma.h.

◆ PW_SVS2

#define PW_SVS2 1

Definition at line 29 of file mini_hexagon_dma.h.

◆ PW_SVS

#define PW_SVS 2

Definition at line 30 of file mini_hexagon_dma.h.

◆ PW_SVS_L1

#define PW_SVS_L1 3

Definition at line 31 of file mini_hexagon_dma.h.

◆ PW_NORMAL

#define PW_NORMAL 4

Definition at line 32 of file mini_hexagon_dma.h.

◆ PW_NORMAL_L1

#define PW_NORMAL_L1 5

Definition at line 33 of file mini_hexagon_dma.h.

◆ PW_TURBO

#define PW_TURBO 6

Definition at line 34 of file mini_hexagon_dma.h.

Typedef Documentation

◆ uint16

typedef uint16_t uint16

Definition at line 10 of file mini_hexagon_dma.h.

◆ uint32

typedef uint32_t uint32

Definition at line 11 of file mini_hexagon_dma.h.

◆ int32

typedef int32_t int32

Definition at line 12 of file mini_hexagon_dma.h.

◆ addr_t

typedef unsigned long addr_t

Definition at line 13 of file mini_hexagon_dma.h.

◆ qurt_size_t

typedef unsigned int qurt_size_t

Definition at line 15 of file mini_hexagon_dma.h.

◆ qurt_mem_pool_t

typedef unsigned int qurt_mem_pool_t

Definition at line 16 of file mini_hexagon_dma.h.

◆ t_stDmaWrapperDmaStats

typedef void* t_stDmaWrapperDmaStats

DMA status Currently not use, for future development.

Definition at line 61 of file mini_hexagon_dma.h.

◆ eDmaWrapper_TransationType

typedef HALIDE_HEXAGON_ENUM eDmaWrapper_TransationType

Initial value:

{
    
    eDmaWrapper_DdrToL2,
    
    eDmaWrapper_L2ToDdr,
} t_eDmaWrapper_TransationType

Transfer type.

Definition at line 66 of file mini_hexagon_dma.h.

◆ t_StDmaWrapper_Roi

typedef struct stDmaWrapper_Roi t_StDmaWrapper_Roi

Roi Properties.

◆ t_StDmaWrapper_FrameProp

typedef struct stDmaWrapper_FrameProp t_StDmaWrapper_FrameProp

Frame Properties.

◆ t_StDmaWrapper_RoiAlignInfo

typedef struct stDmaWrapper_RoiAlignInfo t_StDmaWrapper_RoiAlignInfo

Roi alignment.

◆ t_StDmaWrapper_DmaTransferSetup

typedef struct stDmaWrapper_DmaTransferSetup t_StDmaWrapper_DmaTransferSetup

DmaTransferSetup Properties.

◆ t_DmaWrapper_DmaEngineHandle

typedef void* t_DmaWrapper_DmaEngineHandle

Handle for wrapper DMA engine.

Definition at line 168 of file mini_hexagon_dma.h.

Function Documentation

◆ HAP_cache_lock()

void * HAP_cache_lock	(	unsigned int	size,
		void **	paddr_ptr )

Abstraction for allocation of memory in cache and lock.

API for Cache Allocation

Returns: NULL or Memory

◆ HAP_cache_unlock()

int HAP_cache_unlock ( void * vaddr_ptr )

Abstraction for deallocation of memory and unlock cache.

API for Free

Returns: void

◆ hDmaWrapper_AllocDma()

t_DmaWrapper_DmaEngineHandle hDmaWrapper_AllocDma ( void )

extern

Allocates a DMA Engine to be used by using the default wait type (polling).

Allocates a DMA Engine to be used

Returns: Success: Engine's DMA Handle
Failure: NULL

◆ nDmaWrapper_FreeDma()

int32 nDmaWrapper_FreeDma ( t_DmaWrapper_DmaEngineHandle hDmaHandle )

extern

Frees a DMA Engine that was previously allocated by AllocDma().

Frees a DMA Engine

Parameters

[in] hDmaHandle - Engine's DMA Handle

Returns: Success: OK
Failure: ERR

◆ nDmaWrapper_Move()

int32 nDmaWrapper_Move ( t_DmaWrapper_DmaEngineHandle hDmaHandle )

extern

Starts a transfer on the provided DMA engine.

The transfer is based on descriptors constructed in earlier nDmaWrapper_Prepare() and nDmaWrapper_Update() calls.

Starts a transfer request on the DMA engine

Parameters

[in] hDmaHandle - Engine's DMA Handle

Returns: Success: OK
Failure: ERR

◆ nDmaWrapper_Wait()

int32 nDmaWrapper_Wait ( t_DmaWrapper_DmaEngineHandle hDmaHandle )

extern

Blocks until all outstanding transfers on the DMA are complete.

The wait type is based on the type specified when allocating the engine.

Waits for all outstanding transfers on the DMA to complete

Parameters

[in] hDmaHandle - Engine's DMA Handle

Returns: Success: OK
Failure: ERR

◆ nDmaWrapper_FinishFrame()

int32 nDmaWrapper_FinishFrame ( t_DmaWrapper_DmaEngineHandle hDmaHandle )

extern

This call flushes the DMA buffers.

Blocks until the flush of the DMA is complete.

Cleans up all transfers and flushes DMA buffers

Parameters

[in] hDmaHandle - Engine's DMA Handle

Returns: Success: OK
Failure: ERR

◆ nDmaWrapper_GetRecommendedWalkSize()

int32 nDmaWrapper_GetRecommendedWalkSize	(	t_eDmaFmt	eFmtId,
		bool	bIsUbwc,
		t_StDmaWrapper_RoiAlignInfo *	pStWalkSize )

extern

Get the recommended walk ROI width and height that should be used if walking the entire frame.

The ROI returned is always in terms of frame dimensions. This function is different from nDmaWrapper_GetRecommendedRoi() as coordinates are not used.

Get the recommended walk ROI width and height

Parameters

[in]	eFmtId	- Format ID
[in]	bIsUbwc	- Is the format UBWC (TRUE/FALSE)
[in,out]	pStWalkSize	- Initial walk size, will be overwritten with the recommended walk size to align with DMA requirements

Returns: Success: OK
Failure: ERR

◆ nDmaWrapper_GetDescbuffsize()

int32 nDmaWrapper_GetDescbuffsize	(	t_eDmaFmt *	aeFmtId,
		uint16	nsize )

extern

Calculates the HW descriptor buffer size based on the formats that will be used with the engine.

Get the HW descriptor buffer size per DMA engine

Parameters

[in]	aeFmtId	- Array of format IDs, such as eDmaFmt_NV12, eDmaFmt_NV12_Y, eDmaFmt_NV12_UV etc..
[in]	nsize	- Number of format IDs provided

Returns: Descriptor buffer size in bytes

◆ nDmaWrapper_GetRecommendedIntermBufStride()

int32 nDmaWrapper_GetRecommendedIntermBufStride	(	t_eDmaFmt	eFmtId,
		t_StDmaWrapper_RoiAlignInfo *	pStRoiSize,
		bool	bIsUbwc )

extern

Get the recommended (minimum) intermediate buffer stride for the L2 Cache that is used transfer data from/to DDR.

The stride is greater than or equal to the width and must be a multiple of 256.

Get the recommended intermediate buffer stride.

Parameters

[in]	eFmtId	- Format ID
[in]	pStRoiSize	- The ROI that will be used (should be aligned with the DMA requirements for the format)
[in]	bIsUbwc	- Is the format UBWC (TRUE/FALSE)

Returns: Success: The intermediate buffer stride in pixels
Failure: ERR

◆ nDmaWrapper_GetRecommendedIntermBufSize()

int32 nDmaWrapper_GetRecommendedIntermBufSize	(	t_eDmaFmt	eFmtId,
		bool	bUse16BitPaddingInL2,
		t_StDmaWrapper_RoiAlignInfo *	pStRoiSize,
		bool	bIsUbwc,
		uint16	u16IntermBufStride )

extern

Get the recommended intermediate buffer size for the L2 cache that is used to transfer data to/from DDR.

Get the recommended intermediate buffer size

Parameters

[in]	eFmtId	- Format ID
[in]	bUse16BitPaddingInL2	- Is padding to 16 bits done in the L2 (TRUE/FALSE)
[in]	pStRoiSize	- The ROI that will be used (should be aligned with DMA requirements for the format). The Chroma ROI must follow the standing convention that the provided width and height must be specified in terms of the Luma plane also such that when the width is divided by 2 it specifies the number of interleaved Chroma pixels.
[in]	bIsUbwc	- Is the format UBWC (TRUE/FALSE), note that this should be set to TRUE if either the DDR input or output will be UBWC
[in]	u16IntermBufStride	- The stride (in pixels) to use, the minimum stride may be obtained by calling nDmaWrapper_GetRecommendedIntermBufStride

Returns: Success: The intermediate buffer size in bytes
Failure: ERR

◆ nDmaWrapper_DmaTransferSetup()

int32 nDmaWrapper_DmaTransferSetup	(	t_DmaWrapper_DmaEngineHandle	hDmaHandle,
		t_StDmaWrapper_DmaTransferSetup *	stpDmaTransferParm )

extern

Setup Dma transfer parameters required to be ready to make DMA transfer.

call this API multiple to create a descriptor link list

Dma transfer parameters per HW descriptor

Parameters

[in]	hDmaHandle	- Wrapper's DMA Handle. Represents t_StDmaWrapper_DmaEngine.
[in]	stpDmaTransferParm	- Dma Transfer parameters. Each element describes complete Frame/ROI details for this Dma transfer

Returns: Success: OK Failure: ERR

◆ nDmaWrapper_PowerVoting()

int32 nDmaWrapper_PowerVoting ( uint32 cornercase )

extern

DMA power voting based on Cornercase.

DMA power voting based on Cornercase

Parameters

[in]

cornercase

#define PW_MIN_SVS 0
#define PW_SVS2 1
#define PW_SVS 2
#define PW_SVS_L1 3
#define PW_NORMAL 4
#define PW_NORMAL_L1 5
#define PW_TURBO 6

Returns: Success: OK
Failure: ERR

Variable Documentation

◆ HALIDE_HEXAGON_ENUM

typedef HALIDE_HEXAGON_ENUM {QURT_EOK = 0}

Format IDs.

Definition at line 23 of file mini_hexagon_dma.h.

Classes

Macros

Typedefs

Functions

Variables

Macro Definition Documentation

◆ HALIDE_HEXAGON_ENUM

◆ PW_MIN_SVS

◆ PW_SVS2

◆ PW_SVS

◆ PW_SVS_L1

◆ PW_NORMAL

◆ PW_NORMAL_L1

◆ PW_TURBO

Typedef Documentation

◆ uint16

◆ uint32

◆ int32

◆ addr_t

◆ qurt_size_t

◆ qurt_mem_pool_t

◆ t_stDmaWrapperDmaStats

◆ eDmaWrapper_TransationType

◆ t_StDmaWrapper_Roi

◆ t_StDmaWrapper_FrameProp

◆ t_StDmaWrapper_RoiAlignInfo

◆ t_StDmaWrapper_DmaTransferSetup

◆ t_DmaWrapper_DmaEngineHandle

Function Documentation

◆ HAP_cache_lock()

◆ HAP_cache_unlock()

◆ hDmaWrapper_AllocDma()

◆ nDmaWrapper_FreeDma()

◆ nDmaWrapper_Move()

◆ nDmaWrapper_Wait()

◆ nDmaWrapper_FinishFrame()

◆ nDmaWrapper_GetRecommendedWalkSize()

◆ nDmaWrapper_GetDescbuffsize()

◆ nDmaWrapper_GetRecommendedIntermBufStride()

◆ nDmaWrapper_GetRecommendedIntermBufSize()

◆ nDmaWrapper_DmaTransferSetup()

◆ nDmaWrapper_PowerVoting()

Variable Documentation

◆ HALIDE_HEXAGON_ENUM