Halide 19.0.0
Halide compiler and libraries
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mini_hexagon_dma.h
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1// This header declares the Hexagon DMA API, without depending on the Hexagon SDK.
2
3#ifndef MINI_HEXAGON_DMA_H
4#define MINI_HEXAGON_DMA_H
5
6#ifdef __cplusplus
7extern "C" {
8#endif
9
12typedef int32_t int32;
13typedef unsigned long addr_t;
14
15typedef unsigned int qurt_size_t;
16typedef unsigned int qurt_mem_pool_t;
17#define HALIDE_HEXAGON_ENUM enum __attribute__((aligned(4)))
18
19__inline static int align(int x, int a) {
20 return ((x + a - 1) & (~(a - 1)));
21}
22
23HALIDE_HEXAGON_ENUM{QURT_EOK = 0};
24
25/**
26 * Power Corner vote
27 */
28#define PW_MIN_SVS 0
29#define PW_SVS2 1
30#define PW_SVS 2
31#define PW_SVS_L1 3
32#define PW_NORMAL 4
33#define PW_NORMAL_L1 5
34#define PW_TURBO 6
35
36/**
37 * Format IDs
38 */
40 eDmaFmt_RawData,
41 eDmaFmt_NV12,
42 eDmaFmt_NV12_Y,
43 eDmaFmt_NV12_UV,
44 eDmaFmt_P010,
45 eDmaFmt_P010_Y,
46 eDmaFmt_P010_UV,
47 eDmaFmt_TP10,
48 eDmaFmt_TP10_Y,
49 eDmaFmt_TP10_UV,
50 eDmaFmt_NV124R,
51 eDmaFmt_NV124R_Y,
52 eDmaFmt_NV124R_UV,
53 eDmaFmt_Invalid,
54 eDmaFmt_MAX,
55} t_eDmaFmt;
56
57/**
58 * DMA status
59 * Currently not use, for future development
60 */
62
63/**
64 * Transfer type
65 */
67 /// DDR to L2 transfer
68 eDmaWrapper_DdrToL2,
69 /// L2 to DDR transfer
70 eDmaWrapper_L2ToDdr,
71} t_eDmaWrapper_TransationType;
72
73/**
74 * Roi Properties
75 */
76typedef struct stDmaWrapper_Roi {
77 /// ROI x position in pixels
79 /// ROI y position in pixels
81 /// ROI width in pixels
83 /// ROI height in pixels
86
87/**
88 * Frame Properties
89 */
90typedef struct stDmaWrapper_FrameProp {
91 /// Starting physical address to buffer
93 /// Frame height in pixels
95 /// Frame width in pixels
97 /// Frame stride in pixels
100
101/**
102 * Roi alignment
103 */
105 /// ROI width in pixels
107 /// ROI height in pixels
110
111/**
112 * DmaTransferSetup Properties
113 */
115 /// Frame Width in pixels
117 /// Frame height in pixels
119 /// Frame stride in pixels
121 /// ROI x position in pixels
123 /// ROI y position in pixels
125 /// ROI width in pixels
127 /// ROI height in pixels
129 /// ROI stride in pixels
131 /// Virtual address of the HW descriptor buffer (must be locked in the L2$).
132 void *pDescBuf;
133 /// Virtual address of the TCM pixeldata buffer (must be locked in the L2$).
135 /// Virtual address of the DDR Frame buffer .
137 // UBWC Format
139 /// Should the intermediate buffer be padded. This only apply for 8bit format sucha NV12, NV12-4R
141 /// Format
142 t_eDmaFmt eFmt;
143 /// TransferType: eDmaWrapper_DdrToL2 (Read from DDR), eDmaWrapper_L2ToDDR (Write to DDR);
144 t_eDmaWrapper_TransationType eTransferType;
146
147/**
148 * Abstraction for allocation of memory in cache and lock
149 *
150 * @brief API for Cache Allocation
151 *
152 * @return NULL or Memory
153 */
154void *HAP_cache_lock(unsigned int size, void **paddr_ptr);
155
156/**
157 * Abstraction for deallocation of memory and unlock cache
158 *
159 * @brief API for Free
160 *
161 * @return void
162 */
163int HAP_cache_unlock(void *vaddr_ptr);
164
165/**
166 * Handle for wrapper DMA engine
167 */
169
170/**
171 * Allocates a DMA Engine to be used by using the default wait type (polling).
172 *
173 * @brief Allocates a DMA Engine to be used
174 *
175 * @return Success: Engine's DMA Handle
176 * @n Failure: NULL
177 */
179
180/**
181 * Frees a DMA Engine that was previously allocated by AllocDma().
182 *
183 * @brief Frees a DMA Engine
184 *
185 * @param[in] hDmaHandle - Engine's DMA Handle
186 *
187 * @return Success: OK
188 * @n Failure: ERR
189 */
191
192/**
193 * Starts a transfer on the provided DMA engine. The transfer is based
194 * on descriptors constructed in earlier nDmaWrapper_Prepare() and
195 * nDmaWrapper_Update() calls.
196 *
197 * @brief Starts a transfer request on the DMA engine
198 *
199 * @param[in] hDmaHandle - Engine's DMA Handle
200 *
201 * @return Success: OK
202 * @n Failure: ERR
203 */
205
206/**
207 * Blocks until all outstanding transfers on the DMA are complete.
208 * The wait type is based on the type specified when allocating the
209 * engine.
210 *
211 * @brief Waits for all outstanding transfers on the DMA to complete
212 *
213 * @param[in] hDmaHandle - Engine's DMA Handle
214 *
215 * @return Success: OK
216 * @n Failure: ERR
217 */
219
220/**
221 * This call flushes the DMA buffers. Blocks until the flush of the DMA is complete.
222 *
223 * @brief Cleans up all transfers and flushes DMA buffers
224 *
225 * @param[in] hDmaHandle - Engine's DMA Handle
226 *
227 * @return Success: OK
228 * @n Failure: ERR
229 */
231
232/**
233 * Get the recommended walk ROI width and height that should
234 * be used if walking the entire frame. The ROI returned is always
235 * in terms of frame dimensions. This function is different from
236 * nDmaWrapper_GetRecommendedRoi() as coordinates are not used.
237 *
238 * @brief Get the recommended walk ROI width and height
239 *
240 * @param[in] eFmtId - Format ID
241 * @param[in] bIsUbwc - Is the format UBWC (TRUE/FALSE)
242 * @param[in,out] pStWalkSize - Initial walk size, will be overwritten with
243 * the recommended walk size to align with DMA
244 * requirements
245 *
246 * @return Success: OK
247 * @n Failure: ERR
248 */
249extern int32 nDmaWrapper_GetRecommendedWalkSize(t_eDmaFmt eFmtId, bool bIsUbwc,
250 t_StDmaWrapper_RoiAlignInfo *pStWalkSize);
251
252/**
253 * Calculates the HW descriptor buffer size based on the formats
254 * that will be used with the engine.
255 *
256 * @brief Get the HW descriptor buffer size per DMA engine
257 * @param[in] aeFmtId - Array of format IDs, such as eDmaFmt_NV12, eDmaFmt_NV12_Y,
258 * eDmaFmt_NV12_UV etc..
259 * @param[in] nsize - Number of format IDs provided
260 *
261 * @return Descriptor buffer size in bytes
262 */
263extern int32 nDmaWrapper_GetDescbuffsize(t_eDmaFmt *aeFmtId, uint16 nsize);
264
265/**
266 * Get the recommended (minimum) intermediate buffer stride for the
267 * L2 Cache that is used transfer data from/to DDR. The stride is
268 * greater than or equal to the width and must be a multiple of 256.
269 *
270 * @brief Get the recommended intermediate buffer stride.
271 *
272 * @param[in] eFmtId - Format ID
273 * @param[in] pStRoiSize - The ROI that will be used (should be aligned with
274 * the DMA requirements for the format)
275 * @param[in] bIsUbwc - Is the format UBWC (TRUE/FALSE)
276 *
277 * @return Success: The intermediate buffer stride in pixels
278 * @n Failure: ERR
279 */
281 t_StDmaWrapper_RoiAlignInfo *pStRoiSize,
282 bool bIsUbwc);
283
284/**
285 * Get the recommended intermediate buffer size for the L2 cache
286 * that is used to transfer data to/from DDR.
287 *
288 * @brief Get the recommended intermediate buffer size
289 *
290 * @param[in] eFmtId - Format ID
291 * @param[in] bUse16BitPaddingInL2 - Is padding to 16 bits done in the L2 (TRUE/FALSE)
292 * @param[in] pStRoiSize - The ROI that will be used (should be aligned with
293 * DMA requirements for the format). The Chroma ROI must
294 * follow the standing convention that the provided
295 * width and height must be specified in terms of the
296 * Luma plane also such that when the width is divided
297 * by 2 it specifies the number of interleaved Chroma
298 * pixels.
299 * @param[in] bIsUbwc - Is the format UBWC (TRUE/FALSE), note that this should
300 * be set to TRUE if either the DDR input or output will
301 * be UBWC
302 * @param[in] u16IntermBufStride - The stride (in pixels) to use, the minimum
303 * stride may be obtained by calling
304 * nDmaWrapper_GetRecommendedIntermBufStride
305 *
306 * @return Success: The intermediate buffer size in bytes
307 * @n Failure: ERR
308 */
309extern int32 nDmaWrapper_GetRecommendedIntermBufSize(t_eDmaFmt eFmtId, bool bUse16BitPaddingInL2,
310 t_StDmaWrapper_RoiAlignInfo *pStRoiSize,
311 bool bIsUbwc, uint16 u16IntermBufStride);
312
313/**
314 * Setup Dma transfer parameters required to be ready to make DMA transfer.
315 * call this API multiple to create a descriptor link list
316 *
317 * @brief Dma transfer parameters per HW descriptor
318 *
319 * @param[in] hDmaHandle - Wrapper's DMA Handle. Represents t_StDmaWrapper_DmaEngine.
320 * @param[in] stpDmaTransferParm - Dma Transfer parameters. Each element describes
321 * complete Frame/ROI details for this Dma transfer
322 *
323 * @return Success: OK
324 * Failure: ERR
325 */
327
328/**
329 * DMA power voting based on Cornercase
330 *
331 * @brief DMA power voting based on Cornercase
332 *
333 * @param[in] cornercase:
334 * \code{.cpp}
335 * #define PW_MIN_SVS 0
336 * #define PW_SVS2 1
337 * #define PW_SVS 2
338 * #define PW_SVS_L1 3
339 * #define PW_NORMAL 4
340 * #define PW_NORMAL_L1 5
341 * #define PW_TURBO 6
342 * \endcode
343 *
344 * @return Success: OK
345 * @n Failure: ERR
346 */
348
349#ifdef __cplusplus
350}
351#endif
352
353#endif
void * t_stDmaWrapperDmaStats
DMA status Currently not use, for future development.
HALIDE_HEXAGON_ENUM eDmaWrapper_TransationType
Transfer type.
struct stDmaWrapper_RoiAlignInfo t_StDmaWrapper_RoiAlignInfo
Roi alignment.
int32 nDmaWrapper_GetRecommendedIntermBufSize(t_eDmaFmt eFmtId, bool bUse16BitPaddingInL2, t_StDmaWrapper_RoiAlignInfo *pStRoiSize, bool bIsUbwc, uint16 u16IntermBufStride)
Get the recommended intermediate buffer size for the L2 cache that is used to transfer data to/from D...
unsigned int qurt_mem_pool_t
struct stDmaWrapper_Roi t_StDmaWrapper_Roi
Roi Properties.
int32 nDmaWrapper_FinishFrame(t_DmaWrapper_DmaEngineHandle hDmaHandle)
This call flushes the DMA buffers.
int32 nDmaWrapper_FreeDma(t_DmaWrapper_DmaEngineHandle hDmaHandle)
Frees a DMA Engine that was previously allocated by AllocDma().
struct stDmaWrapper_DmaTransferSetup t_StDmaWrapper_DmaTransferSetup
DmaTransferSetup Properties.
void * t_DmaWrapper_DmaEngineHandle
Handle for wrapper DMA engine.
unsigned int qurt_size_t
unsigned long addr_t
void * HAP_cache_lock(unsigned int size, void **paddr_ptr)
Abstraction for allocation of memory in cache and lock.
t_DmaWrapper_DmaEngineHandle hDmaWrapper_AllocDma(void)
Allocates a DMA Engine to be used by using the default wait type (polling).
int32 nDmaWrapper_PowerVoting(uint32 cornercase)
DMA power voting based on Cornercase.
int32 nDmaWrapper_GetDescbuffsize(t_eDmaFmt *aeFmtId, uint16 nsize)
Calculates the HW descriptor buffer size based on the formats that will be used with the engine.
int32 nDmaWrapper_DmaTransferSetup(t_DmaWrapper_DmaEngineHandle hDmaHandle, t_StDmaWrapper_DmaTransferSetup *stpDmaTransferParm)
Setup Dma transfer parameters required to be ready to make DMA transfer.
int32 nDmaWrapper_Wait(t_DmaWrapper_DmaEngineHandle hDmaHandle)
Blocks until all outstanding transfers on the DMA are complete.
int32_t int32
int32 nDmaWrapper_Move(t_DmaWrapper_DmaEngineHandle hDmaHandle)
Starts a transfer on the provided DMA engine.
struct stDmaWrapper_FrameProp t_StDmaWrapper_FrameProp
Frame Properties.
int32 nDmaWrapper_GetRecommendedWalkSize(t_eDmaFmt eFmtId, bool bIsUbwc, t_StDmaWrapper_RoiAlignInfo *pStWalkSize)
Get the recommended walk ROI width and height that should be used if walking the entire frame.
uint16_t uint16
uint32_t uint32
#define HALIDE_HEXAGON_ENUM
Format IDs.
int32 nDmaWrapper_GetRecommendedIntermBufStride(t_eDmaFmt eFmtId, t_StDmaWrapper_RoiAlignInfo *pStRoiSize, bool bIsUbwc)
Get the recommended (minimum) intermediate buffer stride for the L2 Cache that is used transfer data ...
int HAP_cache_unlock(void *vaddr_ptr)
Abstraction for deallocation of memory and unlock cache.
signed __INT32_TYPE__ int32_t
unsigned __INT16_TYPE__ uint16_t
unsigned __INT32_TYPE__ uint32_t
DmaTransferSetup Properties.
uint16 u16RoiX
ROI x position in pixels.
void * pTcmDataBuf
Virtual address of the TCM pixeldata buffer (must be locked in the L2$).
uint16 u16RoiY
ROI y position in pixels.
t_eDmaWrapper_TransationType eTransferType
TransferType: eDmaWrapper_DdrToL2 (Read from DDR), eDmaWrapper_L2ToDDR (Write to DDR);.
uint16 u16RoiStride
ROI stride in pixels.
void * pDescBuf
Virtual address of the HW descriptor buffer (must be locked in the L2$).
uint16 u16RoiH
ROI height in pixels.
uint16 u16FrameStride
Frame stride in pixels.
uint16 bUse16BitPaddingInL2
Should the intermediate buffer be padded. This only apply for 8bit format sucha NV12,...
uint16 u16FrameH
Frame height in pixels.
uint16 u16RoiW
ROI width in pixels.
void * pFrameBuf
Virtual address of the DDR Frame buffer .
uint16 u16FrameW
Frame Width in pixels.
uint16 u16W
Frame width in pixels.
addr_t aAddr
Starting physical address to buffer.
uint16 u16Stride
Frame stride in pixels.
uint16 u16H
Frame height in pixels.
uint16 u16W
ROI width in pixels.
uint16 u16H
ROI height in pixels.
Roi Properties.
uint16 u16H
ROI height in pixels.
uint16 u16W
ROI width in pixels.
uint16 u16Y
ROI y position in pixels.
uint16 u16X
ROI x position in pixels.