Halide
Halide::Internal::Dim Struct Reference

The Dim struct represents one loop in the schedule's representation of a loop nest. More...

#include <Schedule.h>

Public Member Functions

bool is_pure () const
 Can this loop be evaluated in any order (including in parallel)? Equivalently, are there no data hazards between evaluations of the Func at distinct values of this var? More...
 
bool is_rvar () const
 Did this loop originate from an RVar (in which case the bounds of the loops are algorithmically meaningful)? More...
 
bool is_unordered_parallel () const
 Could multiple iterations of this loop happen at the same time, with reads and writes interleaved in arbitrary ways according to the memory model of the underlying compiler and machine? More...
 
bool is_parallel () const
 Could multiple iterations of this loop happen at the same time? Vectorized and GPULanes loop types are parallel but not unordered, because the loop iterations proceed together in lockstep with some well-defined outcome if there are hazards. More...
 

Public Attributes

std::string var
 Name of the loop variable. More...
 
ForType for_type
 How are the loop values traversed (e.g. More...
 
DeviceAPI device_api
 On what device does the body of the loop execute (e.g. More...
 
DimType dim_type
 The DimType tells us what transformations are legal on this loop (see the DimType enum above). More...
 

Detailed Description

The Dim struct represents one loop in the schedule's representation of a loop nest.

Definition at line 380 of file Schedule.h.

Member Function Documentation

◆ is_pure()

bool Halide::Internal::Dim::is_pure ( ) const
inline

Can this loop be evaluated in any order (including in parallel)? Equivalently, are there no data hazards between evaluations of the Func at distinct values of this var?

Definition at line 397 of file Schedule.h.

References dim_type, Halide::Internal::PureRVar, and Halide::Internal::PureVar.

◆ is_rvar()

bool Halide::Internal::Dim::is_rvar ( ) const
inline

Did this loop originate from an RVar (in which case the bounds of the loops are algorithmically meaningful)?

Definition at line 403 of file Schedule.h.

References dim_type, Halide::Internal::ImpureRVar, and Halide::Internal::PureRVar.

◆ is_unordered_parallel()

bool Halide::Internal::Dim::is_unordered_parallel ( ) const
inline

Could multiple iterations of this loop happen at the same time, with reads and writes interleaved in arbitrary ways according to the memory model of the underlying compiler and machine?

Definition at line 411 of file Schedule.h.

References for_type, and Halide::Internal::is_unordered_parallel().

◆ is_parallel()

bool Halide::Internal::Dim::is_parallel ( ) const
inline

Could multiple iterations of this loop happen at the same time? Vectorized and GPULanes loop types are parallel but not unordered, because the loop iterations proceed together in lockstep with some well-defined outcome if there are hazards.

Definition at line 419 of file Schedule.h.

References for_type, and Halide::Internal::is_parallel().

Member Data Documentation

◆ var

std::string Halide::Internal::Dim::var

Name of the loop variable.

Definition at line 382 of file Schedule.h.

◆ for_type

ForType Halide::Internal::Dim::for_type

How are the loop values traversed (e.g.

unrolled, vectorized, parallel)

Definition at line 385 of file Schedule.h.

Referenced by is_parallel(), and is_unordered_parallel().

◆ device_api

DeviceAPI Halide::Internal::Dim::device_api

On what device does the body of the loop execute (e.g.

Host, GPU, Hexagon)

Definition at line 388 of file Schedule.h.

◆ dim_type

DimType Halide::Internal::Dim::dim_type

The DimType tells us what transformations are legal on this loop (see the DimType enum above).

Definition at line 392 of file Schedule.h.

Referenced by is_pure(), and is_rvar().


The documentation for this struct was generated from the following file: