Halide 19.0.0
Halide compiler and libraries
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mini_cuda.h
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1#ifndef HALIDE_MINI_CUDA_H
2#define HALIDE_MINI_CUDA_H
3
4namespace Halide {
5namespace Runtime {
6namespace Internal {
7namespace Cuda {
8
9#if defined(WINDOWS) && defined(BITS_32)
10#define CUDAAPI __stdcall
11#else
12#define CUDAAPI
13#endif
14
15#ifdef BITS_64
16typedef unsigned long long CUdeviceptr;
17#else
18typedef unsigned int CUdeviceptr;
19#endif
20
21typedef int CUdevice; /**< CUDA device */
22typedef struct CUctx_st *CUcontext; /**< CUDA context */
23typedef struct CUmod_st *CUmodule; /**< CUDA module */
24typedef struct CUfunc_st *CUfunction; /**< CUDA function */
25typedef struct CUstream_st *CUstream; /**< CUDA stream */
26typedef struct CUevent_st *CUevent; /**< CUDA event */
27typedef struct CUarray_st *CUarray;
28
42
43typedef enum {
100
101typedef enum {
102 CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK = 1, /**< Maximum number of threads per block */
103 CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X = 2, /**< Maximum block dimension X */
104 CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y = 3, /**< Maximum block dimension Y */
105 CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z = 4, /**< Maximum block dimension Z */
106 CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X = 5, /**< Maximum grid dimension X */
107 CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y = 6, /**< Maximum grid dimension Y */
108 CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z = 7, /**< Maximum grid dimension Z */
109 CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK = 8, /**< Maximum shared memory available per block in bytes */
110 CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK = 8, /**< Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK */
111 CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY = 9, /**< Memory available on device for __constant__ variables in a CUDA C kernel in bytes */
112 CU_DEVICE_ATTRIBUTE_WARP_SIZE = 10, /**< Warp size in threads */
113 CU_DEVICE_ATTRIBUTE_MAX_PITCH = 11, /**< Maximum pitch in bytes allowed by memory copies */
114 CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK = 12, /**< Maximum number of 32-bit registers available per block */
115 CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK = 12, /**< Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK */
116 CU_DEVICE_ATTRIBUTE_CLOCK_RATE = 13, /**< Typical clock frequency in kilohertz */
117 CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT = 14, /**< Alignment requirement for textures */
118 CU_DEVICE_ATTRIBUTE_GPU_OVERLAP = 15, /**< Device can possibly copy memory and execute a kernel concurrently. Deprecated. Use instead CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT. */
119 CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT = 16, /**< Number of multiprocessors on device */
120 CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT = 17, /**< Specifies whether there is a run time limit on kernels */
121 CU_DEVICE_ATTRIBUTE_INTEGRATED = 18, /**< Device is integrated with host memory */
122 CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY = 19, /**< Device can map host memory into CUDA address space */
123 CU_DEVICE_ATTRIBUTE_COMPUTE_MODE = 20, /**< Compute mode (See CUcomputemode for details) */
124 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH = 21, /**< Maximum 1D texture width */
125 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH = 22, /**< Maximum 2D texture width */
126 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT = 23, /**< Maximum 2D texture height */
127 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH = 24, /**< Maximum 3D texture width */
128 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT = 25, /**< Maximum 3D texture height */
129 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH = 26, /**< Maximum 3D texture depth */
130 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH = 27, /**< Maximum 2D layered texture width */
131 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT = 28, /**< Maximum 2D layered texture height */
132 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS = 29, /**< Maximum layers in a 2D layered texture */
133 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH = 27, /**< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH */
134 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT = 28, /**< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT */
135 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES = 29, /**< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS */
136 CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT = 30, /**< Alignment requirement for surfaces */
137 CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS = 31, /**< Device can possibly execute multiple kernels concurrently */
138 CU_DEVICE_ATTRIBUTE_ECC_ENABLED = 32, /**< Device has ECC support enabled */
139 CU_DEVICE_ATTRIBUTE_PCI_BUS_ID = 33, /**< PCI bus ID of the device */
140 CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID = 34, /**< PCI device ID of the device */
141 CU_DEVICE_ATTRIBUTE_TCC_DRIVER = 35, /**< Device is using TCC driver model */
142 CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE = 36, /**< Peak memory clock frequency in kilohertz */
143 CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH = 37, /**< Global memory bus width in bits */
144 CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE = 38, /**< Size of L2 cache in bytes */
145 CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR = 39, /**< Maximum resident threads per multiprocessor */
146 CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT = 40, /**< Number of asynchronous engines */
147 CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING = 41, /**< Device shares a unified address space with the host */
148 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH = 42, /**< Maximum 1D layered texture width */
149 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS = 43, /**< Maximum layers in a 1D layered texture */
150 CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER = 44, /**< Deprecated, do not use. */
151 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH = 45, /**< Maximum 2D texture width if CUDA_ARRAY3D_TEXTURE_GATHER is set */
152 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT = 46, /**< Maximum 2D texture height if CUDA_ARRAY3D_TEXTURE_GATHER is set */
153 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE = 47, /**< Alternate maximum 3D texture width */
154 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE = 48, /**< Alternate maximum 3D texture height */
155 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE = 49, /**< Alternate maximum 3D texture depth */
156 CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID = 50, /**< PCI domain ID of the device */
157 CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT = 51, /**< Pitch alignment requirement for textures */
158 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH = 52, /**< Maximum cubemap texture width/height */
159 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH = 53, /**< Maximum cubemap layered texture width/height */
160 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS = 54, /**< Maximum layers in a cubemap layered texture */
161 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH = 55, /**< Maximum 1D surface width */
162 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH = 56, /**< Maximum 2D surface width */
163 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT = 57, /**< Maximum 2D surface height */
164 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH = 58, /**< Maximum 3D surface width */
165 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT = 59, /**< Maximum 3D surface height */
166 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH = 60, /**< Maximum 3D surface depth */
167 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH = 61, /**< Maximum 1D layered surface width */
168 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS = 62, /**< Maximum layers in a 1D layered surface */
169 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH = 63, /**< Maximum 2D layered surface width */
170 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT = 64, /**< Maximum 2D layered surface height */
171 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS = 65, /**< Maximum layers in a 2D layered surface */
172 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH = 66, /**< Maximum cubemap surface width */
173 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH = 67, /**< Maximum cubemap layered surface width */
174 CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS = 68, /**< Maximum layers in a cubemap layered surface */
175 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH = 69, /**< Maximum 1D linear texture width */
176 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH = 70, /**< Maximum 2D linear texture width */
177 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT = 71, /**< Maximum 2D linear texture height */
178 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH = 72, /**< Maximum 2D linear texture pitch in bytes */
179 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH = 73, /**< Maximum mipmapped 2D texture width */
180 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT = 74, /**< Maximum mipmapped 2D texture height */
181 CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR = 75, /**< Major compute capability version number */
182 CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR = 76, /**< Minor compute capability version number */
183 CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH = 77, /**< Maximum mipmapped 1D texture width */
184 CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED = 78, /**< Device supports stream priorities */
185 CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED = 79, /**< Device supports caching globals in L1 */
186 CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED = 80, /**< Device supports caching locals in L1 */
187 CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR = 81, /**< Maximum shared memory available per multiprocessor in bytes */
188 CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR = 82, /**< Maximum number of 32-bit registers available per multiprocessor */
189 CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY = 83, /**< Device can allocate managed memory on this system */
190 CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD = 84, /**< Device is on a multi-GPU board */
191 CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID = 85, /**< Unique id for a group of devices on the same multi-GPU board */
194
201
202typedef struct CUDA_MEMCPY3D_st {
203 size_t srcXInBytes; /**< Source X in bytes */
204 size_t srcY; /**< Source Y */
205 size_t srcZ; /**< Source Z */
206 size_t srcLOD; /**< Source LOD */
207 CUmemorytype srcMemoryType; /**< Source memory type (host, device, array) */
208 const void *srcHost; /**< Source host pointer */
209 CUdeviceptr srcDevice; /**< Source device pointer */
210 CUarray srcArray; /**< Source array reference */
211 void *reserved0; /**< Must be NULL */
212 size_t srcPitch; /**< Source pitch (ignored when src is array) */
213 size_t srcHeight; /**< Source height (ignored when src is array; may be 0 if Depth==1) */
214
215 size_t dstXInBytes; /**< Destination X in bytes */
216 size_t dstY; /**< Destination Y */
217 size_t dstZ; /**< Destination Z */
218 size_t dstLOD; /**< Destination LOD */
219 CUmemorytype dstMemoryType; /**< Destination memory type (host, device, array) */
220 void *dstHost; /**< Destination host pointer */
221 CUdeviceptr dstDevice; /**< Destination device pointer */
222 CUarray dstArray; /**< Destination array reference */
223 void *reserved1; /**< Must be NULL */
224 size_t dstPitch; /**< Destination pitch (ignored when dst is array) */
225 size_t dstHeight; /**< Destination height (ignored when dst is array; may be 0 if Depth==1) */
226
227 size_t WidthInBytes; /**< Width of 3D memory copy in bytes */
228 size_t Height; /**< Height of 3D memory copy */
229 size_t Depth; /**< Depth of 3D memory copy */
231
232#define CU_POINTER_ATTRIBUTE_CONTEXT 1
233
234} // namespace Cuda
235} // namespace Internal
236} // namespace Runtime
237} // namespace Halide
238
239#endif
struct CUarray_st * CUarray
Definition mini_cuda.h:27
struct CUevent_st * CUevent
CUDA event.
Definition mini_cuda.h:26
struct CUmod_st * CUmodule
CUDA module.
Definition mini_cuda.h:23
enum Halide::Runtime::Internal::Cuda::CUmemorytype_enum CUmemorytype
struct CUfunc_st * CUfunction
CUDA function.
Definition mini_cuda.h:24
struct CUstream_st * CUstream
CUDA stream.
Definition mini_cuda.h:25
struct CUctx_st * CUcontext
CUDA context.
Definition mini_cuda.h:22
struct Halide::Runtime::Internal::Cuda::CUDA_MEMCPY3D_st CUDA_MEMCPY3D
enum Halide::Runtime::Internal::Cuda::CUjit_option_enum CUjit_option
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH
Maximum 2D linear texture width.
Definition mini_cuda.h:176
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT
Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT.
Definition mini_cuda.h:134
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH
Maximum 2D linear texture pitch in bytes.
Definition mini_cuda.h:178
@ CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y
Maximum grid dimension Y.
Definition mini_cuda.h:107
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH
Maximum 1D linear texture width.
Definition mini_cuda.h:175
@ CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS
Device can possibly execute multiple kernels concurrently.
Definition mini_cuda.h:137
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH
Maximum 2D surface width.
Definition mini_cuda.h:162
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT
Maximum 2D texture height.
Definition mini_cuda.h:126
@ CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE
Peak memory clock frequency in kilohertz.
Definition mini_cuda.h:142
@ CU_DEVICE_ATTRIBUTE_CLOCK_RATE
Typical clock frequency in kilohertz.
Definition mini_cuda.h:116
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH
Maximum mipmapped 1D texture width.
Definition mini_cuda.h:183
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT
Maximum mipmapped 2D texture height.
Definition mini_cuda.h:180
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS
Maximum layers in a 1D layered surface.
Definition mini_cuda.h:168
@ CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY
Device can allocate managed memory on this system.
Definition mini_cuda.h:189
@ CU_DEVICE_ATTRIBUTE_COMPUTE_MODE
Compute mode (See CUcomputemode for details)
Definition mini_cuda.h:123
@ CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID
PCI device ID of the device.
Definition mini_cuda.h:140
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH
Maximum 2D texture width if CUDA_ARRAY3D_TEXTURE_GATHER is set.
Definition mini_cuda.h:151
@ CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT
Alignment requirement for textures.
Definition mini_cuda.h:117
@ CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD
Device is on a multi-GPU board.
Definition mini_cuda.h:190
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS
Maximum layers in a cubemap layered texture.
Definition mini_cuda.h:160
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT
Maximum 2D linear texture height.
Definition mini_cuda.h:177
@ CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X
Maximum block dimension X.
Definition mini_cuda.h:103
@ CU_DEVICE_ATTRIBUTE_MAX_PITCH
Maximum pitch in bytes allowed by memory copies.
Definition mini_cuda.h:113
@ CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT
Number of asynchronous engines.
Definition mini_cuda.h:146
@ CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT
Alignment requirement for surfaces.
Definition mini_cuda.h:136
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH
Maximum cubemap layered texture width/height.
Definition mini_cuda.h:159
@ CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT
Pitch alignment requirement for textures.
Definition mini_cuda.h:157
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH
Maximum 2D texture width.
Definition mini_cuda.h:125
@ CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING
Device shares a unified address space with the host.
Definition mini_cuda.h:147
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS
Maximum layers in a 2D layered texture.
Definition mini_cuda.h:132
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH
Maximum 2D layered surface width.
Definition mini_cuda.h:169
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH
Maximum 3D texture width.
Definition mini_cuda.h:127
@ CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH
Global memory bus width in bits.
Definition mini_cuda.h:143
@ CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR
Minor compute capability version number.
Definition mini_cuda.h:182
@ CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE
Size of L2 cache in bytes.
Definition mini_cuda.h:144
@ CU_DEVICE_ATTRIBUTE_WARP_SIZE
Warp size in threads.
Definition mini_cuda.h:112
@ CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR
Maximum shared memory available per multiprocessor in bytes.
Definition mini_cuda.h:187
@ CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK
Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK.
Definition mini_cuda.h:115
@ CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z
Maximum grid dimension Z.
Definition mini_cuda.h:108
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT
Maximum 2D layered texture height.
Definition mini_cuda.h:131
@ CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z
Maximum block dimension Z.
Definition mini_cuda.h:105
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH
Maximum 3D surface depth.
Definition mini_cuda.h:166
@ CU_DEVICE_ATTRIBUTE_GPU_OVERLAP
Device can possibly copy memory and execute a kernel concurrently.
Definition mini_cuda.h:118
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH
Maximum cubemap texture width/height.
Definition mini_cuda.h:158
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES
Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS.
Definition mini_cuda.h:135
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH
Maximum cubemap layered surface width.
Definition mini_cuda.h:173
@ CU_DEVICE_ATTRIBUTE_INTEGRATED
Device is integrated with host memory.
Definition mini_cuda.h:121
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH
Maximum 1D surface width.
Definition mini_cuda.h:161
@ CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID
Unique id for a group of devices on the same multi-GPU board.
Definition mini_cuda.h:191
@ CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER
Deprecated, do not use.
Definition mini_cuda.h:150
@ CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK
Maximum shared memory available per block in bytes.
Definition mini_cuda.h:109
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS
Maximum layers in a cubemap layered surface.
Definition mini_cuda.h:174
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH
Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH.
Definition mini_cuda.h:133
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT
Maximum 2D layered surface height.
Definition mini_cuda.h:170
@ CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR
Maximum number of 32-bit registers available per multiprocessor.
Definition mini_cuda.h:188
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH
Maximum 3D texture depth.
Definition mini_cuda.h:129
@ CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK
Maximum number of 32-bit registers available per block.
Definition mini_cuda.h:114
@ CU_DEVICE_ATTRIBUTE_TCC_DRIVER
Device is using TCC driver model.
Definition mini_cuda.h:141
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH
Maximum 1D layered texture width.
Definition mini_cuda.h:148
@ CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED
Device supports caching globals in L1.
Definition mini_cuda.h:185
@ CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X
Maximum grid dimension X.
Definition mini_cuda.h:106
@ CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED
Device supports stream priorities.
Definition mini_cuda.h:184
@ CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK
Maximum number of threads per block.
Definition mini_cuda.h:102
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH
Maximum 2D layered texture width.
Definition mini_cuda.h:130
@ CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR
Major compute capability version number.
Definition mini_cuda.h:181
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS
Maximum layers in a 1D layered texture.
Definition mini_cuda.h:149
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH
Maximum 1D texture width.
Definition mini_cuda.h:124
@ CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID
PCI domain ID of the device.
Definition mini_cuda.h:156
@ CU_DEVICE_ATTRIBUTE_PCI_BUS_ID
PCI bus ID of the device.
Definition mini_cuda.h:139
@ CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR
Maximum resident threads per multiprocessor.
Definition mini_cuda.h:145
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH
Maximum 1D layered surface width.
Definition mini_cuda.h:167
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH
Maximum mipmapped 2D texture width.
Definition mini_cuda.h:179
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT
Maximum 2D texture height if CUDA_ARRAY3D_TEXTURE_GATHER is set.
Definition mini_cuda.h:152
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT
Maximum 3D texture height.
Definition mini_cuda.h:128
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT
Maximum 3D surface height.
Definition mini_cuda.h:165
@ CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED
Device supports caching locals in L1.
Definition mini_cuda.h:186
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT
Maximum 2D surface height.
Definition mini_cuda.h:163
@ CU_DEVICE_ATTRIBUTE_ECC_ENABLED
Device has ECC support enabled.
Definition mini_cuda.h:138
@ CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT
Number of multiprocessors on device.
Definition mini_cuda.h:119
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH
Maximum cubemap surface width.
Definition mini_cuda.h:172
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE
Alternate maximum 3D texture height.
Definition mini_cuda.h:154
@ CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK
Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK.
Definition mini_cuda.h:110
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH
Maximum 3D surface width.
Definition mini_cuda.h:164
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE
Alternate maximum 3D texture width.
Definition mini_cuda.h:153
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS
Maximum layers in a 2D layered surface.
Definition mini_cuda.h:171
@ CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY
Memory available on device for constant variables in a CUDA C kernel in bytes.
Definition mini_cuda.h:111
@ CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE
Alternate maximum 3D texture depth.
Definition mini_cuda.h:155
@ CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY
Device can map host memory into CUDA address space.
Definition mini_cuda.h:122
@ CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT
Specifies whether there is a run time limit on kernels.
Definition mini_cuda.h:120
@ CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y
Maximum block dimension Y.
Definition mini_cuda.h:104
This file defines the class FunctionDAG, which is our representation of a Halide pipeline,...
@ Internal
Not visible externally, similar to 'static' linkage in C.
size_t WidthInBytes
Width of 3D memory copy in bytes.
Definition mini_cuda.h:227
CUmemorytype srcMemoryType
Source memory type (host, device, array)
Definition mini_cuda.h:207
size_t Height
Height of 3D memory copy.
Definition mini_cuda.h:228
size_t srcPitch
Source pitch (ignored when src is array)
Definition mini_cuda.h:212
CUdeviceptr srcDevice
Source device pointer.
Definition mini_cuda.h:209
const void * srcHost
Source host pointer.
Definition mini_cuda.h:208
CUarray dstArray
Destination array reference.
Definition mini_cuda.h:222
size_t srcHeight
Source height (ignored when src is array; may be 0 if Depth==1)
Definition mini_cuda.h:213
CUdeviceptr dstDevice
Destination device pointer.
Definition mini_cuda.h:221
size_t dstHeight
Destination height (ignored when dst is array; may be 0 if Depth==1)
Definition mini_cuda.h:225
CUmemorytype dstMemoryType
Destination memory type (host, device, array)
Definition mini_cuda.h:219
size_t dstXInBytes
Destination X in bytes.
Definition mini_cuda.h:215
void * dstHost
Destination host pointer.
Definition mini_cuda.h:220
size_t dstPitch
Destination pitch (ignored when dst is array)
Definition mini_cuda.h:224
CUarray srcArray
Source array reference.
Definition mini_cuda.h:210